CALL_TABLE @ 0xF1A5 table: 4 (SetClocksRatio) >> execute BBA2 (len 110, WS 8, PS 0) SET_ATI_PORT @ 0xBBA8 port: 1 (PLL) CLEAR_WS @ 0xBBAB dst: WS[0x00].[31:0] <- 0x00000000 CLEAR_WS @ 0xBBAE dst: WS[0x01].[31:0] <- 0x00000000 MOVE_WS @ 0xBBB1 src: REG[0x0004].[15:0] -> 0x0DA8 dst: WS[0x01].[15:0] <- 0x0DA8 AND_WS @ 0xBBB6 dst: WS[0x01].[15:0] -> 0x0DA8 src: IMM 0x1FE0 dst: WS[0x01].[15:0] <- 0x0DA0 ADD_WS @ 0xBBBB dst: WS[0x01].[15:0] -> 0x0DA0 src: IMM 0x0020 dst: WS[0x01].[15:0] <- 0x0DC0 MUL_WS @ 0xBBC0 src1: WS[0x01].[15:0] -> 0x0DC0 src2: IMM 0x0008 MOVE_WS @ 0xBBC5 src: WS[0x40].[15:0] -> 0x6E00 dst: WS[0x01].[15:0] <- 0x6E00 MOVE_WS @ 0xBBC9 src: REG[0x0000].[15:0] -> 0x12EC dst: WS[0x00].[15:0] <- 0x12EC AND_WS @ 0xBBCE dst: WS[0x00].[15:0] -> 0x12EC src: IMM 0x1FE0 dst: WS[0x00].[15:0] <- 0x12E0 ADD_WS @ 0xBBD3 dst: WS[0x00].[15:0] -> 0x12E0 src: IMM 0x0020 dst: WS[0x00].[15:0] <- 0x1300 MUL_WS @ 0xBBD8 src1: WS[0x00].[15:0] -> 0x1300 src2: IMM 0x0006 MOVE_WS @ 0xBBDD src: WS[0x40].[15:0] -> 0x7200 dst: WS[0x00].[15:0] <- 0x7200 DIV_WS @ 0xBBE1 src1: WS[0x01].[31:0] -> 0x00006E00 src2: WS[0x00].[31:0] -> 0x00007200 SET_ATI_PORT @ 0xBBE5 port: 2 (MC) MOVE_REG @ 0xBBE8 src: WS[0x40].[7:0] -> 0x00 dst: REG[0xFE15].[15:8] <- 0x00 SHIFT_RIGHT_WS @ 0xBBED dst: WS[0x00].[31:0] -> 0x00007200 shift: 5 dst: WS[0x00].[31:0] <- 0x00000390 DIV_WS @ 0xBBF1 src1: WS[0x01].[31:0] -> 0x00006E00 src2: WS[0x00].[31:0] -> 0x00000390 AND_WS @ 0xBBF5 dst: WS[0x40].[15:0] -> 0x001E src: IMM 0x001F dst: WS[0x40].[15:0] <- 0x001E SHIFT_LEFT_WS @ 0xBBFA dst: WS[0x40].[15:0] -> 0x001E shift: 2 dst: WS[0x40].[15:0] <- 0x0078 SET_DATA_BLOCK @ 0xBBFE block: 24 base: 0xB322 ADD_WS @ 0xBC00 dst: WS[0x42].[15:0] -> 0xB322 src: IMM 0x0004 dst: WS[0x42].[15:0] <- 0xB326 ADD_WS @ 0xBC05 dst: WS[0x42].[15:0] -> 0xB326 src: WS[0x40].[15:0] -> 0x0078 dst: WS[0x42].[15:0] <- 0xB39E MOVE_REG @ 0xBC09 src: ID[0x0000+B39E].[31:0] -> 0xFF7FFF7F dst: REG[0xFE16].[31:0] <- 0xFF7FFF7F EOT @ 0xBC0F